Higher performance, lower cost, increased miniaturization of semiconductor components, and greater packing density of integrated circuit are ongoing goals of the semiconductor industry. Integrated circuit (IC) processing/fabrication is used to produce transistors having various structures including recessed access device (RAD), Fin field effect transistor (FinFET), pseudo silicon on insulator (PSOI), and nanowire, etc., for use in dynamic random access memory (DRAM), NOR and NAND Flash memory, and floating body memory, among other semiconductor devices.
IC processing for memory and other semiconductor devices are currently performed on silicon wafers having a top surface of (100) crystal plane. This surface structures was chosen over the previously used (111) crystal plane because of its comparatively low surface state density on thermally oxidized surfaces. For example, in the diamond lattice of silicon the (111) plane is more densely packed than the (100) plane, and thus etch rates of {111} orientated surfaces are expected to be lower than those with {100} orientation. Bonding orientation of the different planes also contributes to etchant selectivity to exposed planes. One etchant that exhibits such orientation dependent etching properties consists of a mixture of KOH and isopropyl alcohol. For example, such a mixture may etch about one hundred times faster along (100) planes than along (111) planes.
Various chemistries have been used to etch silicon. For example, both single crystal and polycrystalline silicon may be wet etched in mixtures of nitric acid (HNO3) and hydrofluoric acid (HF). With use of such etchants, the etching may be isotropic. The reaction is initiated by the HNO3, which forms a layer of silicon dioxide on the silicon, and the HF dissolves the silicon oxide away. In some cases, water is used to dilute the etchant, with acetic acid (CH3COOH) used as a buffering agent.
Wafers having the top surface of {100} crystal plane are currently provided with a registration mark in the orthogonal <110> direction. IC processing of the wafer is then performed using this <110> registration mark. Hence, masks are aligned along the <110> direction.
Integrated circuitry can be fabricated relative to one or both of bulk semiconductor substrates, such as silicon wafers, and semiconductor on insulator (SOI) substrates. SOI forms a semiconductor layer, e.g., silicon, onto an insulator, e.g., silicon dioxide. One method of forming SOI circuitry, at least in part, includes epitaxially growing single crystalline silicon electively from a single crystalline surface. Unfortunately in some instances epitaxially grown silicon tends to form crystalline defects, known as dislocations and stacking faults, which can result in undesired leakage within or between the resulting fabricated devices.